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Hierarchical defect-oriented fault simulation for digital circuits

  1. TitleHierarchical defect-oriented fault simulation for digital circuits
    Author Blyzniuk M.
    Co-authors Cibáková Tatiana 1960- SAVINFO - Ústav informatiky SAV

    Gramatová Elena 1949- SAVINFO - Ústav informatiky SAV    SCOPUS    RID

    Kuzmicz W.

    Lobur M.

    Pleskacz W.

    Raik J.

    Ubar R.

    Source document IEEE European Test Workshop. Order No. PROO390 (2000), p. 69-74. - Los Alamitos, California : IEEE Computer Society
    Languageeng - English
    CountryUS - United States of America
    Document kindrozpis článkov z periodík (rzb)
    CitationsAHMAD, A. - AL-ABRI, D. Design of a dynamic test tool in the area of digital system testing. In International Conference on Communication, Computer and Power - icccp´09. ISSN 1813-419X. 2009, p. 9-12.
    CategoryADC
    Year2000
    Registered inWOS
    article

    article

    rok vydaniarok metrikyIFIF Q (best)SJRSJR Q (best)
    2000
Number of the records: 1  

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