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Hierarchical defect-oriented fault simulation for digital circuits
Title Hierarchical defect-oriented fault simulation for digital circuits Author Blyzniuk M. Co-authors Cibáková Tatiana 1960- SAVINFO - Ústav informatiky SAV Gramatová Elena 1949- SAVINFO - Ústav informatiky SAV SCOPUS RID Kuzmicz W. Lobur M. Pleskacz W. Raik J. Ubar R. Source document ETW 2000 - Informal Digest : IEEE European Test Workshop. P. 151-156 / Prinetto P. ; Teixiera J.P. ; Teixiera I.M.C. ; Flottes M.L.. - Los Alamitos : IEEE, 2000 Language eng - English Document kind rozpis článkov z periodík (rzb) Citations AHMAD, A. - AL-ABRI, D. - AL-RAMHI, M.M. Design of an e-learning process in the area of digital system testing. In Proceedings International Conference on Distance Education (ICODE2006). 2006, pp. 27-31. AHMAD, A. - AL-ABRI, D. Design of a realistic test simulator for a built-in self test environment. In Journal of Engineering Research. ISSN 17266009, 2010-12-01, 7, 2, pp. 69-79. Category AFC - Published papers from foreign scientific conferences Year 2000 article
rok vydania rok metriky IF IF Q (best) SJR SJR Q (best) 2000
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