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Hierarchical test generation for combinational circuits with real defects coverage
Title Hierarchical test generation for combinational circuits with real defects coverage Author Cibáková Tatiana 1960- SAVINFO - Ústav informatiky SAV Co-authors 1955- Fischerová Mária SAVINFO - Ústav informatiky SAV SCOPUS Gramatová Elena 1949- SAVINFO - Ústav informatiky SAV SCOPUS RID Kuzmicz W. Pleskacz W. Raik J. Ubar R. Source document Microelectronics reliability. No. 42 (2002), s. 1141-1149 Language eng - English Country US - United States of America Document kind rozpis článkov z periodík (rbx) Citations SHANG, Qing H. - WU, Li H. - XIANG, Fu J. Structure-based multi-fault test generation algorithm for combinational circuit. In Journal of Harbin Institute of Technology (New Series). ISSN 10059113, 2006-08-01, 13, 4, pp. 452-454. COSTA, A.L.T. - de BARROS NAVINER, L.A. Modelling stuck-at faults in combinational circuits with generalized stochastic Petri nets. In Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT'10). 2010, 4 p. WIELGUS, Andrzej - POTRYKUS, Bartosz. Resistive Shorts Characterization in CMOS Standard Cells for Test Pattern Generation. In ELECTRON TECHNOLOGY CONFERENCE 2013. ISSN 0277-786X, 2013, vol. 8902, no., pp. KRENZ-BAATH, Rene - GLOWATZ, Andreas - HAPKE, Friedrich. Fault Collapsing of Multi-Conditional Faults. In PROCEEDINGS OF THE 2013 IEEE 16TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2013, vol., no., pp. 42-47. ZHANG, Lijun - WANG, Ziou - LI, Youzhong - MAO, Lingfeng. A Precise Design for Testing High-Speed Embedded Memory using a BIST Circuit. In IETE JOURNAL OF RESEARCH. ISSN 0377-2063, 2017, vol. 63, no. 4, pp. 473-481. Category ADCA - Scientific papers in foreign journals registered in Current Contents Connect with IF (impacted) Year 2002 Registered in WOS Registered in SCOPUS Registered in CCC DOI 10.1016/S0026-2714(02)00080-X 
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