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Test pattern generation for the combinational representation of asynchronous circuits
Title Test pattern generation for the combinational representation of asynchronous circuits Author Dobai Roland 1983- SAVINFO - Ústav informatiky SAV SCOPUS RID Co-authors Gramatová Elena 1949- SAVINFO - Ústav informatiky SAV SCOPUS RID Source document / Kotásek Zdeněk ; Steininger Andreas ; Gramatová Elena 1949- ; Zimmermann Horst ; Armengaud Eric ; Vierhaus Heinrich T. ; Függer Matthias ; Lechner Jakob 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems : 13th IEEE DDECS 2010. P. 323-328. - Vienna : Institute of Electrical and Electronics Engineers, 2010 ; IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems IEEE DDECS 2010 Language eng - English Country AT - Austria Document kind rozpis článkov z periodík (rzb) Citations DABHI, J.B. Design a pattern generator with low switching activity to test complex combinational logic with high test coverage. In International Journal of Research in Computer and Communication Technology. 2015, vol. 4, no. 4, pp. 286-291. KHATRI, Abdul Rafay - HAYEK, Ali - BOERCOEK, Josef. ATPG Method with a Hybrid Compaction Technique for Combinational Digital Systems. In Proceedings of the 2016 SAI Computing Conference (SAI), 2016, vol., no., pp. 924-930. KHATRI, Abdul Rafay - HAYEK, Ali - BÖRCSÖK, Josef. Validation of selecting SP-values for fault models under proposed RASP-FIT tool. In 2017 1st International Conference on Latest Trends in Electrical Engineering and Computing Technologies, INTELLECT 2017, 2018-01-31, 2018-January, pp. 1-7. Category AEC - Scientific papers in foreign peer-reviewed proceedings, monographs Category of document (from 2022) V2 - Vedecký výstup publikačnej činnosti ako časť editovanej knihy alebo zborníka Type of document príspevok Year 2010 Registered in WOS Registered in SCOPUS DOI 10.1109/DDECS.2010.5491759 
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