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MBIST for LEON3 processor core cache
Title MBIST for LEON3 processor core cache Author Kincel Andrej SAVINFO - Ústav informatiky SAV SCOPUS Co-authors Baláž Marcel 1979- SAVINFO - Ústav informatiky SAV SCOPUS RID Source document / Sekanina Lukáš ; Fey Görschwin ; Růžička Richard ; Raik J. ; Aunet Snorre 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems : DDECS. P. 287-288. - Brno : IEEE Computer Society Test Technology Technical Council, 2013 ; 2013 IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS Language eng - English Country CZ - Czech Republic Document kind rozpis článkov z periodík (rzb) Citations BANERJEE, Arijit - BREIHOLZ, Jacob - CALHOUN, Benton H. A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations. In Proceedings of the Custom Integrated Circuits Conference. ISSN 08865930, 2015-11-25, 2015-November, pp. BANERJEE, A. Ultra-low-power embedded SRAM design for battery-operated and energy-harvested IoT applications. In Green Electronics. IntechOpen. 2018, pp. 127-145. http://dx.doi.org/10.5772/intechopen.76765 KARA, Cavit - ASLAN, A. Burak - HALUK CANBERI, M. Test Software for National Satellite On-Board Computer. In 2020 Turkish National Software Engineering Symposium, UYMS 2020 Proceedings, 2020-10-07, pp. GHALE, Suraj B. - NAMITA, P. Design and Implementation of Memory BIST for Hybrid Cache Architecture. In Proceedings of the 6th International Conference on Communication and Electronics Systems, ICCES 2021, 2021-07-08, pp. 26-31. Dostupné na: https://doi.org/10.1109/ICCES51350.2021.9489225. Category ADMB - Scientific papers in foreign non-impacted journals registered in Web of Sciences or Scopus Category of document (from 2022) V3 - Vedecký výstup publikačnej činnosti z časopisu Type of document článok Year 2013 Registered in WOS Registered in SCOPUS DOI 10.1109/DDECS.2013.6549836 
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