Case study: BISR for a processor multiplier

Number of the records: 1

Title	Case study: BISR for a processor multiplier
Author	Kincel Andrej SAVINFO - Ústav informatiky SAV ^SCOPUS
Co-authors	Baláž Marcel 1979- SAVINFO - Ústav informatiky SAV ^SCOPUS ^RID

Source document	Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems : DDECS. P. 314-317. - Piscataway : IEEE, 2014 / Pleskacz W. ; Renovell M. ; Kasprowicz Dominik ; Sekanina Lukáš ; Bernard Serge
Language	eng - English
Country	US - United States of America
Document kind	rozpis článkov z periodík (rzb)
Category	ADMB - Scientific papers in foreign non-impacted journals registered in Web of Sciences or Scopus
Category of document (from 2022)	V3 - Vedecký výstup publikačnej činnosti z časopisu
Type of document	článok
Year	2014
Registered in	WOS
Registered in	SCOPUS
DOI	10.1109/DDECS.2014.6868818

article

rok	CC	IF	IF Q (best)	JCR Av Jour IF Perc	SJR	SJR Q (best)	CiteScore
	N

rok vydania	rok metriky	IF	IF Q (best)	SJR	SJR Q (best)
2014

Number of the records: 1