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Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement
Title Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement Author Krištofík Štefan 1984- SAVINFO - Ústav informatiky SAV SCOPUS RID ORCID Co-authors Baláž Marcel 1979- SAVINFO - Ústav informatiky SAV SCOPUS RID Malík Peter 1980 - SAVINFO - Ústav informatiky SAV SCOPUS RID ORCID Source document Microelectronics reliability. Vol. 86 (2018), p. 38-53 Language eng - English Document kind rozpis článkov z periodík (rbx) Citations BONCALO, Oana - AMARICAI, Alexandru - LENDEK, Zsofia. Fault Tolerant Digital Data-Path Design via Control Feedback Loops. In ELECTRONICS, 2020, vol. 9, no. 10, pp. BUKOV, V. N. - SHURMAN, V. A. - AGEEV, A. M. Algorithms for Managing the Redundancy of Onboard Equipment Complexes of Mobile Objects. Part 2. Paired Arbitration of Computers. In Mekhatronika, Avtomatizatsiya, Upravlenie, 2022-01-01, 23, 6, pp. 327-336. ISSN 16846427. Dostupné na: https://doi.org/10.17587/mau.23.327-336. Category ADCA - Scientific papers in foreign journals registered in Current Contents Connect with IF (impacted) Category of document (from 2022) V3 - Vedecký výstup publikačnej činnosti z časopisu Type of document článok Year 2018 Registered in WOS Registered in SCOPUS Registered in CCC DOI 10.1016/j.microrel.2018.04.010 article
File name Access Size Downloaded Type License Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement.pdf available 2.1 MB 0 Publisher's version rok CC IF IF Q (best) JCR Av Jour IF Perc SJR SJR Q (best) CiteScore A rok vydania rok metriky IF IF Q (best) SJR SJR Q (best) 2018 2017 1.236 Q3 0.388 Q2
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