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Handbook of testing electronic systems
Názov Handbook of testing electronic systems Autor Novák Ondřej Spoluautori Gramatová Elena 1949- SAVINFO - Ústav informatiky SAV SCOPUS RID Ubar Raimund Vyd.údaje Praha : České vysoké učení technické v Praze , 2005. - 395 s. Jazyk dok. eng - angličtina Krajina CZ - Česká republika Druh dok. knihy Ohlasy SEKANINA, Lukas. Evolution of polymorphic self-checking circuits. In EVOLVABLE SYSTEMS: FROM BIOLOGY TO HARDWARE, PROCEEDINGS. ISSN 0302-9743, 2007, vol. 4684, no., pp. 186-197. SEKANINA, Lukas. Design and analysis of a new self-testing adder which utilizes polymorphic gates. In PROCEEDINGS OF THE 2007 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2007, vol., no., pp. 243-246. HAHANOV, Vladimir - GUZ, Olesya - KULBAKOVA, Natalya - DAVYDOV, Maxim. Vector-logical diagnosis method for SOC functionalities. In Proceedings of IEEE East-West Design and Test Symposium, EWDTS'08, 2008-12-01, pp. 159-162. PLESKACZ, Witold A. - STOPJAKOVA, Viera - BOREJKO, Tomasz - JUTMAN, Artur - WALKANIS, Andrzej. DefSim: A remote laboratory for studying physical defects in CMOS digital circuits. In IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. ISSN 0278-0046, 2008, vol. 55, no. 6, pp. 2405-2415. ŠAFÁŘ, P. Návrh nelineárních celulárních automatů. Diplomová práce. 2008, 30 p. DOBAI, R. Testovanie asynchrónnych digitálnych obvodov. In Počítačové architektury a diagnostika (PAD 2010). Eds K. Vlček, L. Běhal, J. Giesl a kol. - Zlín. Univerzita Tomáše Bati ve Zlíne. ISBN 978-80-7318-847-4. 2009, pp. 57-62. HAHANOV, Vladimir - VASILENKO, Vasilina - KULBAKOVA, Natalya - GHARIBI, Wajeb. Vector-Logical Approach to Diagnosis of SOC Components. In EXPERIENCE OF DESIGNING AND APPLICATION OF CAD SYSTEMS IN MICROELECTRONICS, 2009, vol., no., pp. 301-304. CHEBYKINA, Natalia V. - MOSIN, Sergey G. A technique of optimal built-in self-test circuitries generation. In Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10, 2010-12-01, pp. 145-148. SEKANINA, L. Evoluční návrh hardware. In Umelá inteligencia a kognitívna veda II. ISBN 978-80-227-3284-0. 2010, pp. 437-465. REPINSKI, U. Malicious fault list generation for digital systems. In Master thesis. University of Tallinn, Dept. of Computer Engineering. 2010. 31 p. DOBAI, R. Automatický generátor testovacích vektorov pre asynchrónne obvody. In Počítačové architektury a diagnostika (PAD 2009). Eds Z. Kotásek, M. Bidlo, J. Jaroš - Brno, Vysoké učení technické v Brně. ISBN 978-80-214-4140-8. 2010, pp. 147-152. MOSIN, Sergey G. - CHEBYKINA, Natalia V. - SERINA, Maria S. Technique of LFSR based test generator synthesis for deterministic and pseudorandom testing. In 2011 11th International Conference The Experience of Designing and Application of CAD Systems in Microelectronics, CADSM 2011, 2011-05-13, pp. 128-131. DOBAI, R. Test generation of asynchronous sequential digital circuits. In Information Science and Technologies Bulletin of the ACM Slovakia. ISSN 1338-1237. 2011, vol. 3, no. 1, pp. 73-83. HAHANOV, Vladimir. Infrastructure Intellectual Property for SoC Simulation and Diagnosis Service. In DESIGN OF DIGITAL SYSTEMS AND DEVICES. ISSN 1876-1100, 2011, vol. 79, no., pp. 289-330. SEKANINA, Lukáš. Evolution of digital circuits. In Genetic and Evolutionary Computation Conference, GECCO'11 Companion Publication, 2011-08-26, pp. 1343-1359. PFEIFER, P. Fault-tolerance and testability of programmable devices in safety applications with increased lifetime and reliability rewuirements. In Počítačové architektúty a diagnostika - PAD 2011. ISBN 978-80-227-3552-0. 2011, pp. 14-19. DRAHOŇOVSKÝ, T. Využití částečné dynamické rekonfigurace pro testování a zvyšování spolehlivosti FPGA obvodů. In Počítačové architektúty a diagnostika - PAD 2011. ISBN 978-80-227-3552-0. 2011, pp. 55-60. KOAL, T. - KOTHE, R. - VIERHAUS, H.T. SoC self test based on a test-processor. In Design and Test Technology for Dependable System-on-Chip, 2011, pp. 360-376. SCHÖLZEL, M. Self-testing and self-repairing embedded processors: Techniques for statically scheduled superscalar architectures. Habilitation Thesis. Brandenburg University of Technology Cottbus-Senftenberg. 2014, 277 p. BAGHDADI, A.A.A. - CHACHANOV, V.I. – Litvinova, E.I. Metody analiza i diagnostirovanija cifrovych ustrojstv. (Digital system analysis and diagnosis methods - analytical review). In Avtomatizirovannye sistemy upravlenija i pribory avtomatiki. 2014, no. 166, pp. 59-74. KRIŠTOFÍK, Š. Príspevok k architektúram a algoritmom samočinnej opravy pamätí RAM. Dizertačná práca. FIIT STU, Bratislava. 2015, 121 p. SIEBERT, M. Metódy testovania porúch oneskorení na kritických cestách v digitálnych systémoch. Dizertačná práca. FIIT STU, Bratislava. 2015, 105 p. DOBRUCKÝ, B. - SINDLER, P. - CUNTALA, J. - KONDELOVA, A. Increasing of reliability of FPGA implemented microcontroller using the error self correcting techniques. In Journal of Communication and Computer. doi: 10.17265/1548-7709/2015.05.00. 2015, vol. 12, pp. 219-227. KRISTOFIK, Stefan - BALAZ, Marcel - MALIK, Peter. Hardware redundancy architecture based on reconfigurable logic blocks with persistent high reliability improvement. In MICROELECTRONICS RELIABILITY. ISSN 0026-2714, 2018, vol. 86, no., pp. 38-53. PRIYADARSHINI, K.M. - AGARWAL, V. - RAVINDRAN, R.E. - ROMITHA, K.M. - KANCHAN, P. - HARSHITA, K. Logical fault modelling algorithm for stuck-at-fault. In International Journal of Recent Technology and Engineering (IJRTE). ISSN 2277-3878, 2020, vol. 8, no. 5, pp. 4302-4306. Kategória AAA - Vedecké monografie vydané v zahraničných vydavateľstvách Kategória (od 2022) V1 - Vedecký výstup publikačnej činnosti ako celok Typ výstupu monografia Rok vykazovania 2005 Odkazy (4) Publikačná činnosť SAV - články 
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